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 NTE7153 Integrated Circuit Vertical Deflection Output Circuit
Description: The NTE7153 is a vertical deflection output integrated circuit in a 7-Lead SIP type package designed for use in TV and CRT displays with excellent image quality that use a BUS control system signal processing IC. This device can drive the direct (even including a DC component) deflection yoke with the sawtooth wave output from the BUS control system signal processing IC. Because the maximum deflection current is 2.2AP-P, the NTE7153 is suitable for use in large screen sets. Features: D Low Power Dissipation due to Built-In Pump-Up Circuit D Vertical Output Circuit D Thermal Protection Circuit Built-In D Excellent Crossover Characteristics D DC Coupling Possible Absolute Maximum Ratings: (TA = +25C unless otherwise specified) Maximum Supply Voltage, VCC6 max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34V Output Block Supply Voltage, VCC3 max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70V Deflection Output Current, I2max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5 to +1.5AP-O Allowable Power Dissipation (With Arbitraily Large Heat Sink), PDmax . . . . . . . . . . . . . . . . . . . . 9W Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 to +85C Storage Temperature Range, Tstgv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +150C Thermal Resistance, Junction-to-Case, RthJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4C/W Recommended Operation Conditions: (TA = +25C unless otherwise specified)
Parameter Recommended Supply Voltage Operating Supply Voltage Range Recommended Deflection Output Current Symbol VCC6 VCC6 op I2P-P Test Conditions Min - 16 - Typ 24 - - Max - 33 2.2 Unit V V AP-P
Electrical Characteristics: (VCC6 = 24V, TA = +25C unless otherwise specified)
Parameter Pump-Up Charge Saturation Voltage Pump-Up Discharge Saturation Voltage Deflection Output Saturation Voltage (Lower) Deflection Output Saturation Voltage (Upper) Idling Current Midpoint Voltage Symbol VS7-1 VS6-7 VS2-1 VS3-2 IDL VMID
Pin Connection Diagram (Front View)
Test Conditions I7 = 20mA I7 = -1.1A I2 = 1.1A I2 = -1.1A
Min - - - - 35 11
Typ - - - - - 12
Max 1.8 3.2 1.5 3.5 65 13
Unit V V V V mA V
7 Pump-Up Output 6 VCC 5 Inverting Input 4 Non-Inverting Input 3 Output Stage VCC 2 Ver. Output 1 GND
.708 (18.0)
.118 (3.0)
.590 (15.0) .527 (13.4) .425 (10.8)
1
7
.228 (5.8)
.100 (2.54)


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